Description: Description: Description: C:\Users\Joint Director\images\maintopFinal.jpg

 

4

7

 

Chip Designing (28th. Batch)

(FPGA based Digital System Design by using Verilog HDL)

This Course uses the "Course & Go" concept. This concept combines Consultancy, Design and Education. For you it means that you just get what you need to know for your Digital System Design. You will not loose time listening to topics, which are far away from your practical application. The relevant knowledge is transferred in an interactive and intensive way. Finally Basic aim of this Course is to make a professional capable enough to make his/her own FPGA based systems. This course covers design simulation, verification/testing and synthesis/implementation of FPGA based digital systems using the standard Verilog Hardware Description Language and Synthesis Tool.  

This course is heavily Laboratory oriented in which the participants will be designed and evaluated digital circuits. Computer Aided Design (CAD) tools will be used for the experiments.

Course Outlines:

  Digital Design Methodology

  Digital Chip Design using Verilog HDL with Model / Sim Simulator

  Controller based Designs - State Machines

  Testing and Verification Methodology - Automated Test Benches

  Xilinx FPGA Design Methodology

  Xilinx FPGA/CPLD architecture Spartan-II & Spartan-III devices

  Design synthesis and implementation Using Xilinx ISE-13.1

  Timing Analyzer, Core Generator, Constraint Editor, Floor Planner, X Power and iMPACT tools

  Synthesis and Implementation design Flow for Xilinx Technology

  Real time on-chip debugging for Xilinx FPGA by using Chipscope Pro Tools

  Analyze design statistics, connectivity, timing and placement result by using PlanAhead

  Strategy for Explore Critical Path of Design back to RTL

  Real Time simulation with Xilinx FPGA based Training Boards

  Introduction of Embedded Controllers in FPGAs (Embedded Development Kit) and Xilinx System Generator

 

 

Attention:

Already 520 Engineers/Scientists, mostly from Defense Organizations, have successfully completed this course under Skill Development Council (SDC), Govt. of Pakistan. 

Prerequisites:

         B.E Electronics / Electrical, Computer / IT Engineering, M.Sc Electronics / Computer Science    (Students are warmly welcome)

         Basic Fundamental of Digital Design & Computer Architecture

         Programming Basics (prefer C language) 

* Opportunity for Fresh Engineers to improve their skills in High Tech field of Electronics

Skill Gained after completing this course 

After completing this comprehensive training, participant will have the necessary skills to: 

         Locate the design issues and solve them

         Implement digital designs using Verilog HDL

         Create test and verification strategy for chip designing

         Design an optimize state machine based designs

         Xilinx FPGA architecture details

         Synthesis, Implementation & configuration processes using ISE 9.2i

         Create design constraints and analyze synthesis & timing reports

         Use built-in resources of Xilinx FPGA in your design

         How to use Xilinx FPGA on PCB (FPGA configuration on Board)

         Use Xilinx Chip Scope Pro tools for real-time debugging

         Use Xilinx Plan Ahead tools for Advance Implementation Process

         Create Real-time testing environment with FPGA

  Course Schedule

This lab-course introduces the Verilog HDL language with emphasis on targeting Xilinx devices specifically general. This lab work also combines insightful lecture with practical lab exercises to reinforce key then apply this information to any digital design using a Top-Down synthesis design approach along with proper test and verification methodologies. 

For FPGA Implementation tackles the most sophisticated aspects of the ISE Suite, ModelSim SE and Xilinx hardware. Twenty labs provide hands-on experience in this course. In addition, by mastering the tools and the design methodologies presented in this course, you will be able to create your design faster, shorten your development time, and lower development costs.

  

 

Duration

Detail

Duration

Six Weeks

Two days per week

Lectures

Sixteen (16)

Two hrs per lecture

LABs

Twenty (20)

Two hrs per lab

 1st Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

1. Course Introduction.

 

2. Design Methodology, Digital Design 

    Objective, Combinational & 

    Sequential Design Basics, Clock 

    Methodology, Critical & Cycle Time

2 hrs

 

 

ModelSim Tool Training

2

2 hrs

1. Verilog HDL Basics, Verilog Value 

    Set, Numbers in Verilog, Net, Register  

    & Vectors, Arrays, Memories,  

    Parameters, Strings, System tasks,

    Compiler Directives In Verilog

 

2. Abstraction Levels (Switch, Gate,

    Dataflow & Behavioral), Modules

    & Ports, Module instances,

    Hierarchal Design Concept, Gate

    Level Modeling using Examples

 

2 hrs

 

Simulation of 1-bit ADDER/SUB  

    using Gate Level & Data Flow  

    Level in ModelSim

 

Simulation of 1-bit 

     MUX/DEMUX using Gate Level  

     & Data Flow Level in ModelSim

 

Simulation of 4-bit UX/DEMUX   

     using 1-bit in ModelSim

 

3

2 hrs

 

1. Continuous Assignment, Port

    Assignments, Operators (Logical,

    Bitwise, Reduction, Shift,

    Concatenation, Relational,

    Equality, Conditional, Arithmetic)

 

2. Behavioral Modeling, Procedural

    Blocks (initial, always)

2 hrs

 

Simulation of 4-bit ADDER/SUB   

    using bit in  ModelSim

 

Simulation of implementation of  

    Timing Diagrams, D-FF/Register

    and 4-bit Ripple Carry Counter in  

    ModelSim

 

2nd Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

 

1. Blocking & Non-Blocking

    Assignments, Clock & Async

    / Sync Reset in Digital System

    Events, Combinatorial

    Statements, Timing Analysis,

    Delays

 

2. Procedural Statements (if, 

    case/casex/casez, for, while, repeat, 

    forever), Mixed abstraction modeling

 

2 hrs

 

Design a Single/Dual Clock RAM

     and  simulate in ModelSim

 

Design a FIFO and simulate in 

    ModelSim

2

2 hrs

 

1. Test Bench Concept, Formation of

    Test Bench, File Handling, Tasks,   

    Functions, Test Drivers / Vectors, 

    Built-  in Self-Test, Boundary 

    Scan Testing

 

2. System Tasks, Compiler Directives,

    Parameters/Define Statements

 

2 hrs

 

Generate random data & use File 

    Handling using Tasks to improve  

    testability by using ModelSim

3

2 hrs

 

1. Digital Systems, State Machine  

    Concept, Moore & Mealy State 

    Machines based Design, One Hot  

    State Machine

 

2. State machine based Traffic  

    Controller

 

2 hrs

 

Traffic Controller

 

3rd Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

 

1. Behavioral/RTL Coding Techniques 

    (Synchronous / Asynchronous Design,  

    Race Condition, Delay Dependent

    Logic, Glitches, Hold Time

    Violations, Gated Clocking),

    Simulation /     Synthesis Issues

2 hrs

 

Design an ADC  Interface  with 

    FPGA and Simulate in ModelSim

 

2

2 hrs

1. Comparison of HDL:

    Verilog HDL Vs VHDL

 

2. RTL Coding Guidelines

2 hrs

 

Design a DAC Interface with

     FPGA  and Simulate in ModelSim

 

3

2 hrs

 

1. Introduction of FPGA & CPLD, FPGA

    & CPLD basics, Xilinx FPGA series,

    FPGA Technology, FPGA   

    advantages, FPGA variations, FPGA

    Configurable Logic Blocks (CLBs), 

    LUT Implementation in CLBs,

    FPGA IO Blocks

 

2. Xilinx XC4000 & Spartan Series

    FPGA internal architecture

2 hrs

 

Design a DSP Processor

    (Ti TMSC64x) Interface with

    FPGA and Simulate in ModelSim

 

4th Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

 

1. Xilinx FPGA Design Process,

    Synthesis Flow (Xilinx Synthesis  

    Technology),

2. Core Generator

 

 

2 hrs

 

Xilinx ISE Tool Training

    (Overview with Synthesis,

    Implementation and Configuration)

 

Generate a Block RAM for FIFO

      by using ISE 8.1i Core Generator

 

2

2 hrs

 

1. Timing Simulation

 

2. Implementation Flow

    (Translate, MAP and Place &

    Route), Constraint Editor,

    Functional / Timing Verification,

    Floor Planner, FPGA Editor, 

    Configuration Flow (configuration

    modes), EPROM File Formatter,

    iMPACT tool basics

2 hrs

 

Timing Simulation of Dual Clock 

     RAM (with Block & Distributed)

 

Use Constraints Editor , mcs, bit 

     file generation

3

2 hrs

 

1. Concepts of Digital Signal Processing 

    (DSP) in  Field Programmable Gate  

    Array (FPGA)

2 hrs

 

Design a 4-Tap FIR Filter

    and Simulate in ModelSim

 

Use pipelining for increasing  

     design frequency

5th Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

 

1. Concepts of Digital Signal Processing 

    (DSP) in  Field Programmable Gate  

    Array (FPGA)

 

2. DLL blocks in FPGAs

2 hrs

 

Training Board Description

    and Flasher on FPGA Training Kit

 

UP & DOWN Counter and      

    7-Segment Display Panel

    Interface on FPGA Training Kit

 

2

2 hrs

 

1. Introduction to configuration, Xilinx 

    PROM, OTP & In  System 

    Programmable, Configuration Modes,

    Master Serial Mode, Slave Serial

    Mode, SelectMap Mode, JTAG or

    Boundary Scan Mode

 

2. Configuration Modes, Master

    Serial Mode, Slave Serial Mode, 

    SelectMap Mode, JTAG or Boundary

    Scan Mode

 

2 hrs

 

LCD Interface with FPGA

    Training Kit

 

Traffic Controller on   

    FPGA Training Kit

 

3

2 hrs

1. UART-transmitter on FPGA

    Development Board   

2 hrs

 

UART-Receiver  on FPGA 

     Development Board

 

6th Week:

 

DAY

TIME

TOPIC

TIME

LAB WORK

1

2 hrs

 

1. Real time debugging for Xilinx FPGA  

    by using Xilinx ChipScope Pro

 

2 hrs

 

Monitor internal signals of

    UART core by using ChipScope

   

2

2 hrs

1. System-on-Chip Concept

 

2. New Trends in VLSI Industry

2 hrs

 

Monitor internal signals of UART 

    Core by using ChipScope

 

3

2 hrs

Case Study

2 hrs

  Case Study

Note: The Lecture/LAB contents may be changed slightly during the course.

 Optional:* The group of Two/Three participants will be presented their assigned projects with complete RTL, test bench and synthesis results. Projects, which should be state machine based, will be discussed individually with participants.

 

Starting From

Timing

Last Date of Registration

Fee

25-09-2017

(Mon-Tue-Wed)

1700 - 2000

23-09-2017

Rs: 18,000 per participant

 

* 10 % discount for groups only.

 

Duration   = 72 Hours

 

 

 

Description: Description: Description: C:\Users\Joint Director\images\leftPortion.gif

Home | Site Map | Contact Us | About Us

SKILL DEVELOPMENT COUNCIL
Plot No: 205, Korang Road, I-10/3, Islamabad| 051-4440719 / +0331-7888990 - 4
Copyright 2008 Skill Development Council